Digital ASIC Design Engineer
Unisoc (UNISOC Technologies)
- Designed RxDFE subsystem RTL (~<XX>K gates), supporting 3G/4G/5G multi-bandwidth configurations via parameterized link reuse
- Independently implemented DDC datapath (NCO / CIC / HB / FIR), completed fixed-point scheme and passed error analysis review
- Designed AGC and Power Estimation modules, achieving 70 dB dynamic range
- Performed critical path restructuring on 491.52 MHz high-frequency DSP datapath during synthesis and STA, converging timing slack from <-XXX ps> to <+XX ps>; participated in post-layout simulation and ECO closure
- Contributed to successful bring-up of C2/S6/S6P chips, debugging datapath link-level issues
- Explored resource sharing and parameterized design for 5.5G baseband pre-research (up to 600 MHz input)
- Implemented clock gating and bit-width trimming for low-power optimization, reducing dynamic power by ~<XX%>